1. Field of the Invention
The present invention relates to a memory cell, and more particularly, to a non-volatile memory cell comprising a transistor and two plane capacitors, wherein the capacitance of the two plane capacitors are constant when the memory cell operates within in an operating voltage range.
2. Description of the Related Art
A non-volatile memory device is capable of retaining stored information after disconnection of its power source. An EEPROM is a type of non-volatile memory device in which information is written and erased from the memory cell thereof using an electrical signal. Such devices typically utilize floating gate transistors in which the floating gate stores charge when the memory cell is programmed.
FIG. 1 shows a schematic diagram of a single-poly flash EEPROM memory cell 100 disclosed in U.S. Pat. No. 6,191,980. The memory cell 100 includes a PMOS transistor MC1, a NMOS transistor M2 and an eraser M3. The PMOS transistor MC1, the NMOS transistor M2 and the eraser M3 all share a common polysilicon floating gate 206. To further increase the coupling between the control gate and the floating gate, a capacitor C1 is added to the memory cell. Because the EEPROM cell is programmed and erased by transistor structures, a P-well and N-well are both required in the EEPROM cell, however, size thereof is large and a large wafer area is required.